Senior Design Verification Engineer

San Francisco

Responsible for place/route of complex SoCs in advanced process technologies

Define the floorplan, including pin placement, power busing, placement of blocks and macros

Design complex clocking structures

Execute place/route, signal integrity avoidance/fixing, power/clock analysis, timing closure, noise analysis and DRC/LVS

Author: admin

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  • BS, MS in electrical engineering or computer engineering
  • Experience using Synopsys ICC/ICC2 or Cadence Innovus/SOC Encounter
  • Successful tapeout experience of multiple complex chips (10M+ gates) at 28 nm or below
  • Expertise in floorplanning, Physical Synthesis, CTS, Routing
  • Expertise in low power flow (power gating, multi-Vt, voltage islands, dynamic voltage scaling, body biasing, etc)
  • Hands on experience with STA using Primetime, power analysis, DRC/LVS, Noise analysis
  • Understanding of deep sub-micron design problems and solutions (leakage power, signal integrity, DFM etc.)
  • Programming experience in tcl, Perl or C

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Attached Resume